1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Background Art
Semiconductor memory devices such as a dynamic random access memory (DRAM), a floating body cell (FBC), and a ferroelectric memory detect data “0” or “1”, which is stored in a memory cell, by using a reference signal corresponding to an intermediate value between data “0” and data “1”. An intermediate voltage or an intermediate resistance between data “0” and data “1” is used as the reference signal.
There is a method of providing a reference generating circuit that generates a reference signal. According to this method, the reference generating circuit supplies a reference signal which is common to a certain memory cell array. In this case, provision of one reference generating circuit is sufficient for a certain memory cell or for a plurality of memory cell arrays. Therefore, the area of the semiconductor memory device can be made relatively small.
However, because a predetermined reference signal is used in common for memory cell arrays, this has a possibility of a difficulty in identifying data when a threshold value or a resistance of memory cells varies due to changes in temperature and depending on manufacturing processes.
On the other hand, a method of providing a dummy cell in each bit line is available for generating a reference signal. According to this method, a dummy cell that stores data “0” is connected with a dummy cell that stores data “1”, thereby generating an intermediate value between data “0” and data “1”.
For example, a voltage, which is based on a sum of a cell current in a dummy cell that stores data “0” and a cell current in a dummy cell that stores data “1”, is generated as a reference voltage. Further, a voltage based on a current, which is two times a cell current flowing through a memory cell to be detected, is compared with a reference voltage. With this arrangement, the semiconductor memory device can detect data “0” or “1” stored in the memory cell. Because a dummy cell is provided for each bit line, a variation in a threshold value or a resistance of a memory cell causes a variation in a threshold value or resistance of the dummy cell. Therefore, the method using a dummy cell makes it easier to identify data than the method using a reference generating circuit.
However, because the two dummy cells that store data “0” and data “1” respectively are used to generate reference signals, the reference signals have a large variation among them due to changes in temperature and depending on manufacturing processes. It is generally known that when reference signals have a large variation, data detection sensitivity in memory cells is deteriorated. Therefore, in order to further improve the data detection sensitivity, the variation of reference signals needs to be minimized (See Japanese Patent Application Laid-open No. 2003-100080 Publication).